mb9b 4 10r series 32 - bit a rm ? cortex ? - m 3 fm3 microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 document number: 002 - 05615 rev. *d ? 408-943-2600 revised february 9 , 2018 the mb9b 4 10r series are highly integrated 32 - bit microcontrollers dedicated for embedded controllers with high - performance and competitive cost. these series are based on the a rm cortex - m3 processor with on - chip flash memory and sram, and has peripheral functions such as motor control timers, adcs and communication interfaces ( can , uart, csio, i 2 c, lin). the products which are described in this data sheet are placed into type4 pro duct categories in fm3 family peripheral manual. features 32 - bit a rm cortex - m3 core ? processor version: r2p1 ? up to 144mhz frequency operation ? memory protection unit (mpu): improves the reliability of an embedded system ? integrated nested vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management on - chip memories [ flash memory ] these series are based on two independent on - chip flash memories. ? mainflash ? up to 512 kbyte ? built - in flash accelerator system with 16 kbyt e trace buffer memory ? the read access to flash memory can be achieved without wait cycle up to operation frequency of 72 mhz. even at the operation frequency more than 72 mhz, an equivalent access to flash memory can be obtained by flash accelerator system . ? security function for code protection ? workflash ? 32 kbyte ? read cycle ? 4 wait - cycle: the operation frequency more than 72 mhz ? 2 wait - cycle: the operation frequency more than 40 mhz, and to 72 mhz ? 0 wait - cycle: the operation frequency to 40 mhz ? security function is shared with code protection [ sram ] this series contain a total of up to 64 kbyte on - chip sram. this is composed of two independent sram (sram0, sram1). sram0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to sys tem bus. ? sram0: up to 32 kbyte ? sram1: up to 32 kbyte external bus interface ? supports sram, nor and nand flash device ? up to 8 chip selects ? 8 - /16 - bit data width ? up to 25 - bit address bit ? maximum area size: up to 256 mbytes ? supports address/data multiplex ? supp orts external rdy input can interface (max two channels) ? compatible with can specification 2.0a/b ? maximum transfer rate : 1 mbps ? built - in 32 message buffer multi - function serial interface (max eight channels) ? 4 channels with 16 steps9 - bit fifo (ch.4 to ch.7), 4 channels without fifo (ch.0 to ch.3) ? operation mode is selectable from the followings for each channel. ? uart ? csio ? lin ? i 2 c ? uart ? full - duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control: automatically control the transmission by cts/rts (only ch.4) ? various error detect functions available (parity errors, framing errors, and overrun errors) ? c sio ? full - duplex double buffer ? built - in dedicated baud rate generator ? overrun error detect function available
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